R8C2C datasheet(136/615 Pages) RENESAS

136 / 615 page

R8C/2C Group, R8C/2D Group

10. Clock Generation Circuit

Rev.2.00

Dec 05, 2007

Page 115 of 585

REJ09B0339-0200

Figure 10.13 shows the Time from Wait Mode to Interrupt Routine Execution.

When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT

instruction.

(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral

function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function

interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).

(2) Set the I flag to 1.

(3) Operate the peripheral function to be used for exiting wait mode.

When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request

generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register

and the CM07 bit in the CM0 register, as described in Figure 10.13.

The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock

when the WAIT instruction is executed.

Figure 10.13

Time from Wait Mode to Interrupt Routine Execution

(system clock)

(XCIN clock)

(system clock)

(XCIN clock)

Period of CPU clock

× 20 cycles

Same as above

Following total

time is the time

from wait mode

until an interrupt

routine is

executed.

(flash memory

operates)

(flash memory

stops)

Wait mode

Flash memory

activation sequence

CPU clock restart sequence

Interrupt sequence

Interrupt request generated

CM07 Bit

Time for Interrupt

Sequence (T3)

Remarks

FMSTP Bit

FMR0 Register

CM0 Register

Period of system clock

× 12 cycles + 30 µs (max.)

Period of XCIN clock

× 12 cycles + 30 µs (max.)

Period of system clock

× 12 cycles

Period of XCIN clock

× 12 cycles

Time until Flash Memory

is Activated (T1)

Period of CPU clock

× 6 cycles

Same as above

Time until CPU Clock

is Supplied (T2)

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