M32C83T datasheet(378/527 Pages) RENESAS

378 / 527 page

Page 355

22. CAN Module

)

(

22.2 Timing with CAN-Associated Registers

22.2.1 CAN Module Reset Timing

Figure 22.27 shows an operation example of when the CAN module is reset.

(1) The CAN module can be reset when the STATE_RESET bit in the C0STR register is set to "1" (CAN

module reset completed) after the RESET0 and RESET1 bits in the C0CTLR0 register are set to "1"

(CAN module reset).

(2) Set necessary CAN-associated registers.

(3) CAN communication can be established after the STATE_RESET bit is set to "0" (resetting) after

the RESET0 and RESET1 bits are set to "0" (CAN module reset exited) .

Figure 22.27 Example of CAN Module Reset Operation

22.2.2 CAN Transmit Timing

Figure 22.28 shows an operation example of when the CAN transmits a frame.

(1) When the TRMREQ bit is set to "1" (request to transmit the data frame) while the CAN bus is in as

idle state, the TRMACTIVE bit in the C0MCTLi register (i=0 to 15) is set to "1" (during transmis-

sion) and the TRMSTATE bit in the C0STR register is set to "1" (during transmission). The CAN

starts transmitting the frame.

(2) After a CAN frame transmission is completed, the SENTDATA bit in the C0MCTLi register is set to "1"

(already transmitted), the TRMSUCC bit in the C0STR register to "1" (transmission completed) and

the SISi bit in the C0SISTR register to "1" (interrupt requested). The MBOX3 to MBOX0 bits in the

C0STR register store transmitted message slot numbers.

RESET0 bit

"1"

"0"

RESET1 bit

"1"

"0"

STATE_RESET bit

"1"

"0"

CAN counfiguration

Verify the STATE_RESET bit

CAN operation

Set to "1" by program

simultaneously

Operation (1)

Set to "0" by program

simultaneously

Operation (2)

Operation (3)

Verify the STATE_RESET bit

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