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M32C83T Datasheet(PDF) 382 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 382 Page - Renesas Technology Corp |
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382 / 527 page  Page 359 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 23. DRAMC ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M 23. DRAMC The DRAM controller (DRAMC) controls the DRAM area, which ranges from 512 Kbytes to 8 Mbytes. Table 23.1 lists specifications of the DRAMC. Table 23.1 DRAMC Specifications Item Specification DRAM Area 512 KB, 1 MB, 2 MB, 4 MB, 8 MB Bus Control 2CAS/1W Refresh ________ ________ CAS-before-RAS refresh, Self refresh Supported Function Mode EDO, fast page mode Wait State Insertion 1-wait state, 2-wait state Table 23.2 shows pins associated with DRAMC. Signals listed in Table 23.2 are output by setting the AR2 ______ to AR0 bits in the DRAMCONT register for the DRAM area and accessing DRAM. See Table 7.9 for RAS, ________ ________ _____ CASL, CASH and DW signal operations. Figure 23.1 shows the DRAMCONT register and REFCNT regis- ter. Table 23.2 DRAMC-associated Pins Port Bus for Device Access except DRAM(1) Bus for DRAM Access P0 D0 to D7 D0 to D7 P1 D8 to D15 D8 to D15(2) P3 A8 to D15 MA0 to MA7 P40 to P44 A16 to A20 MA8 to MA12 P50 _______ _____ WRL / WR _________ CASL P51 ________ _______ WRH / BHE _________ CASH P52 ____ RD _____ DW P56 ALE _______ RAS NOTES: 1. This is an example of the separate bus and 16-bit data bus. 2. This bus is available when the DS2 bit in the DS register is set to "1" (16-bit data bus) and the PM02 bit ____ _______ _______ in the PM0 register is set to "1" (RD/WRL/WRH in R/W mode). |
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