M32C83T datasheet(384/527 Pages) RENESAS

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Page 361

23. DRAMC

)

(

DRAMC is not available when the PM11 to PM10 bits in the PM1 register are set to "112" (mode 3). Set the

PM11 to PM10 bits to "002," "012" or "102" (mode 0 to 2). When the 16-bit DRAM data bus is selected, set

____

________ ________

the PM02 bit in the PM0 register to "1" (RD/WRH/WRL).

Required wait time between DRAM power-on and memory operation, and necessary processing of dummy

cycle for refresh varies with externally attached DRAM specifications.

23.1 DRAMC Multiplexed Address Output

DRAMC outputs signals, which are multiplexed row addresses and column addresses, to address bus A8 to

A20. Figure 23.2 shows an output format for multiplexed addresses.

23.2 Refresh

23.2.1 Refresh

_______

Refresh method is the CAS-before-RAS refresh. The REFCNT register controls the refresh interval. Re-

fresh signals are not output in a hold state.

The setting value of the REFCNT register is obtained as follows:

The value of the REFCNT register (0016 to FF16) = refresh interval time / (CPU clock frequency X 32) - 1

23.2.2 Self-Refresh

The refresh signal described in 23.2.1 stops while the CPU stops in stop mode, etc. The DRAM self-

refresh function can be activated by setting the self-refresh before the CPU stops. Setting and cancella-

tion procedures for the self-refresh are as follows:

(1) Setting self-refresh (with 1 wait state, 4 Mbytes)

•••

mov.b

#00000001b,DRAMCONT

;Set the AR2 to AR0 bits to "0002" (DRAM disabled)

mov.b

#10001011b,DRAMCONT

;Set the AR2 to AR0 bits again and the SREF bit to "1"

(self-refresh on) simultaneously

nop

;Execute the nop instruction twice

nop

;

•••

(2) Cancellation of self-refresh (with 1 wait state, 4M bytes)

•••

mov.b

#00000001b,DRAMCONT

;Set the AR2 to 0 bits to "0002" (self-refresh cancellation)

and the SREF bit to "0" (DRAM disabled) simultaneously

mov.b

#00001011b,DRAMCONT

;Set the AR2 to AR0 bits again

mov.b

400h, 400h

;DRAM access is disabled immediately after cancellation.

This is an example of a dummy read operation.

•••

_______

Both RAS and CAS are held "L" during self-refresh. When devices other than DRAM are attached, the

______

_____

WR signal is held "L". Take procedures such as applying an "H" signal to the CS.

Figures 23.3 to 23.5 show bus timings during DRAM access.

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