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M32C83T Datasheet(PDF) 385 Page - Renesas Technology Corp

Part # M32C83T
Description  16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  527 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C83T Datasheet(HTML) 385 Page - Renesas Technology Corp

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Page 362
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23. DRAMC
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M
A9
(A20)
(A19)
A18
A17
A16
A15
A14
A13
A12
A11
A10
A0
(A22)
(A22)
A8
A7
A6
A5
A4
A3
A2
A1
(1) In 8-bit Bus Mode
(A9)
(A20)
(A19)
(A18)
(A17)
(A16)
(A15)
(A14)
(A13)
(A12)
(A11)
(A10)
Address used for 512K-byte and 1M-byte DRAM area
Address used for 2M-byte and 4M-byte DRAM area
Address used for 8M-byte DRAM area
MA1
MA12 MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
A9
(A20)
A18
A17
A16
A15
A14
A13
A12
A11
A10
A0
(A22)
A8
A7
A6
A5
A4
A3
A2
A1
A19
A19
A20
A21
A9
A18
A17
A16
A15
A14
A13
A12
A11
A10
A0
(A22)
A8
A7
A6
A5
A4
A3
A2
A1
A19
A21
A22
A20
(A9)
(A20)
(A19)
A18
A17
A16
A15
A14
A13
A12
A11
A10
(A0)
(A22)
(A20)
A8
A7
A6
A5
A4
A3
A2
A1
(2) In 16-bit Bus Mode
(A9)
(A20)
(A19)
(A18)
(A17)
(A16)
(A15)
(A14)
(A13)
(A12)
(A11)
(A10)
Pin Function
MA1
MA12
MA11 MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
(A9)
(A20)
A18
A17
A16
A15
A14
A13
A12
A11
A10
(A0)
(A22)
A8
A7
A6
A5
A4
A3
A2
A1
A19
A9
A9
A20
(A9)
A18
A17
A16
A15
A14
A13
A12
A11
A10
(A0)
A8
A7
A6
A5
A4
A3
A2
A1
Row Address
A19
A9
A21
A20
A22
( ): disabled bits,
:bits which output addresses changed by data bus width and the
DRAM area
–: indetermimate
NOTES:
1. The above applies when using a 4Mx1 or 4Mx4 memory configuration. When using a 4Mx16
configuration, implement the following combinations:
For row addresses, MA0 to MA12; for column addresses, MA2 to MA8, MA11 and MA12.
Or for row addresses, MA1 to MA12; for column addresses, MA2 to MA9, MA11 and MA12.
–
–
(A8)
MA0
–
–
–
–
–
–
(A8)
MA0
–
–
–
–
Row Address
Row Address
Pin Function
Row Address
Row Address
Row Address
Column Address
Column Address
Column Address
Column Address
Column Address
Column Address
Address used for 4M-byte and 8M-byte(1) DRAM area
Address used for 512K-byte DRAM area
Address used for 1M-byte and 2M-byte DRAM area
Figure 23.2 Multiplexed Address Output Pattern



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