M32C83T datasheet(145/527 Pages) RENESAS

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Page 122

12. DMAC

)

(

(1) When 8-bit data is transferred

or when 16-bit data is transferred from an even source address by a 16-bit data bus

BCLK

Address

Bus

RD Signal

WR Signal

Data

Bus

(3) When one wait state is inserted into the source-read bus cycle under the conditions in (1)

(2) When 16-bit data is transferred from an odd source address

or when 16-bit data is transferred from source by an 8-bit data bus

BCLK

Address

Bus

RD Signal

WR Signal

Data

Bus

CPU Use

Source

Source + 1

(4) When one wait state is inserted into the source-read bus cycle under the conditions in (2)

NOTES:

1. The above applies when the destination-write bus cycle is 2 BCLK cycles (1 bus cycle).

However, if the destination-write bus cycle is placed under these conditions, it will change to

the same timing as the source-read bus cycle illustrated above.

Destination

BCLK

Address

Bus

RD Signal

WR Signal

Data

bus

CPU Use

Source

Destination

CPU Clock

Address

Bus

RD Signal

WR Signal

Data

Bus

CPU Use

Source

Source + 1

Destination

CPU Use

Source

Destination

CPU Use

Source

Destination

BCLK

Figure 12.6 Transfer Cycle Examples with the Source-Read Bus Cycle

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