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M32C83T Datasheet(PDF) 146 Page - Renesas Technology Corp

Part # M32C83T
Description  16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  527 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C83T Datasheet(HTML) 146 Page - Renesas Technology Corp

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12. DMAC
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12.2 DMAC Transfer Cycles
The number of DMAC transfer cycle can be calculated as follows.
Any combination of even or odd transfer read and write addresses are possible. Table 12.3 lists the number
of DMAC transfer cycles. Table 12.4 lists coefficient j, k.
Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k
Table 12.3 DMAC Transfer Cycles
Single-Chip Mode
Memory Expansion Mode
Microprocessor Mode
Transfer Unit
Bus Width
Access Address
Read
Write
Read
Write
Cycle
Cycle
Cycle
Cycle
16-bit
Even
1
1
1
1
8-bit transfers
Odd
1
1
1
1
(BWi bit in the DMDp
8-bit
Even
——
11
register = 0)
Odd
——
11
16-bit
Even
1
1
1
1
16-bit transfers
Odd
2
2
2
2
(BWi bit = 1)
8-bit
Even
——
22
Odd
——
22
i= 0 to 3, p = 0 to 1
Table 12.4 Coefficient j, k
12.3 Channel Priority and DMA Transfer Timing
When multiple DMA requests are generated in the same sampling period, between the falling edge of the
CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i = 0 to 3) is set to "1" (requested)
simultaneously. Channel priority in this case is : DMA0 > DMA1 > DMA2 > DMA3.
Figure 12.7 shows an example of the DMA transfer by external factors.
In Figure 12.7, the DMA0 request having the highest priority is received first to start a transfer when a DMA0
request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus
privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts.
After one DMA1 transfer is completed, the privilege is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when
DMA requests, as DMA1 in Figure 12.7, occur more than once before receiving bus privilege, the DRQ bit
is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is
completed.
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