M32C83T datasheet(150/527 Pages) RENESAS

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13. DMACII

)

(

Transfer Mode

(MOD)

Transfer Counter

(COUNT)

Transfer Source Address (or immediate data) (SADR)

Operation Address(1)

(OADR)

Transfer Destination Address

(DADR)

Chained Transfer Address(2)

(CADR0)

Chained Transfer Address(2)

(CADR1)

End-of-Transfer Interrupt Address(3)

(IADR0)

End-of-Transfer Interrupt Address(3)

(IADR1)

16 bits

DMAC II Index

Starting Address (BASE)

BASE + 2

BASE + 4

BASE + 6

BASE + 8

BASE + 10

BASE + 14

BASE + 16

BASE + 12

Transfer Mode

(MOD)

Transfer Counter

(COUNT)

Transfer Source Address

(SADR1)

Transfer Destination Address

(DADR1)

Transfer Source Address

(SADR2)

Transfer Destination Address

(DADR2)

Transfer Source Address

(SADR7)

Transfer Destination Address

(DADR7)

16 bits

BASE

BASE + 2

BASE + 4

BASE + 6

BASE + 8

BASE + 10

BASE + 28

BASE + 30

Memory-to-Memory Transfer, Immediate Transfer,

Calculation Transfer

Multiple Transfer

NOTES:

1. This data is not required when not using the calculation transfer function.

2. This data is not required when not using the chained transfer function.

3. This data is not required when not using the end-of-transfer interrupt.

The DMAC II index must be located on the RAM. Necessary data is set front-aligned. For example, if not using a calculation

transfer function, set destination address to BASE+6. (See Table 13.2)

Starting address of the DMAC II index must be set in the interrupt vector for the peripheral function interrupt causing a DMAC II request.

13.1.2 DMAC II Index

The DMAC II index is a data table which comprises 8 to 18 bytes (maximum 32 bytes when the multiple

transfer function is selected). The DMAC II index stores parameters for transfer mode, transfer counter,

source address (or immediate data), operation address as an address to be calculated, destination ad-

dress, chained transfer address, and end-of-transfer interrupt address.

This DMAC II index must be located on the RAM area.

Figure 13.2 shows a configuration of the DMAC II index. Table 13.2 lists a configuration of the DMAC II

index in transfer mode.

Figure 13.2 DMAC II Index

The followings are details of the DMAC II index. Set these parameters in the specified order listed in

Table 13.2, according to DMAC II transfer mode.

• Transfer mode (MOD)

Two-byte data is required to set transfer mode. Figure 13.3 shows a configuration for transfer mode.

• Transfer counter (COUNT)

Two-byte data is required to set the number of transfer.

• Transfer source address (SADR)

Two-byte data is required to set the source memory address or immediate data.

• Operation address (OADR)

Two-byte data is required to set a memory address to be calculated. Set this data only when using

the calculation transfer function.

• Transfer destination address (DADR)

Two-byte data is required to set the destination memory address.

• Chained transfer address (CADR)

Four-byte data is required to set the starting address of the DMAC II index for the next transfer. Set

this data only when using the chained transfer function.

• End-of-transfer interrupt address (IADR)

Four-byte data is required to set a jump address for end-of-transfer interrupt processing. Set this

data only when using the end-of-transfer interrupt.

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