M32C83T datasheet(182/527 Pages) RENESAS

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Page 159

14. Timer (Timer B)

)

(

Timer Bi Mode Register (i=0 to 5)

(Pulse Period / Pulse Width Measurement Mode)

Symbol

Address

After reset

TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002

(Note 1)

TMOD0

TMOD1

MR0

Operation Mode

Select Bit

MR1

MR3

MR2

TCK0

TCK1

Count Source

Select Bit

0 0 : f1

0 1 : f8

1 0 : f2n(3)

1 1 : fC32

TB0MR, TB3MR registers:

Set to "0" in pulse period/pulse width measurement mode

Timer Bi Overflow Flag(2)

0 : No overflow

1 : Overflow

Measurement Mode

Select Bit

1 0 : Pulse period measurement mode,

pulse width measurement mode

b1 b0

Bit Name

Function

Bit

Symbol

0 0 : Pulse period measurement 1

0 1 : Pulse period measurement 2

1 0 : Pulse width measurement

1 1 : Do not set to this value

b3 b2

b7 b6

NOTES:

1. The MR1 to MR0 bits selects the following measurements.

Pulse period measurement 1 (MR1 to MR0 bits = 002) :

Measures between the falling edge and the next falling edge of a pulse to be measured

Pulse period measurement 2 (MR1 to MR0 bits = 012) :

Measures between the rising edge and the next rising edge of a pulse to be measured

Pulse width measurement (MR1 to MR0 bits = 102) :

Measures between a falling edge and the next rising edge of a pulse to be measured and

between the rising edge and the next falling edge of a pulse to be measured

2. The MR3 bit is indeterminate when reset.

When the timer overflows, the MR3 bit is set to "1" (overflow) simultaneously. When the TBiS bit is

set to "1" (start counting) and the next count source is counted after the MR3 bit is set to "1", the

MR3 bit is set to "0" (no overflow) by writing again.

The MR3 bit cannot be set to "1" by program.

3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).

TB1MR, TB2MR TB4MR, TB5MR registers:

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Figure 14.22 TB0MR to TB5MR Registers

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