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M32C83T Datasheet(PDF) 191 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 191 Page - Renesas Technology Corp |
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191 / 527 page  Page 168 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 15. Three-Phase Motor Control Timer Functions ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M Timer B2 Register(1) Symbol Address After Reset TB2 035516 - 035416 Indeterminate RW RW Function b0 b8 Setting Range If setting value is n, count source is divided by n+1. The timers A1, A2 and A4 start every time an underflow occurs. 000016 to FFFF16 NOTES: 1. Use a 16-bit data for read and write. b15 b7 Trigger Select Register Symbol Address After Reset TRGSR 034316 0016 b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW Bit Name Bit Symbol TA1TGL TA1TGH TA2TGL Timer A1 Event/Trigger Select Bit TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH Function Set to "012" (TB2 underflow) before using a V-phase output control circuit Timer A2 Event/Trigger Select Bit Set to "012" (TB2 underflow) before using a W-phase output control circuit : Selects an input to the TA3IN pin : Selects TB2 overflow(1) : Selects TA2 overflow(1) : Selects TA4 overflow(1) Timer A3 Event/Trigger Select Bit Timer A4 Event/Trigger Select Bit Set to "012" (TB2 underflow) before using a U-phase output control circuit NOTES: 1. Overflow or underflow b5 0 0 1 1 b4 0 1 0 1 Count Start Flag Symbol Address After Reset TABSR 034016 0016 RW RW RW RW RW Bit Name Function Bit Symbol TA0S TA1S TA2S Timer A0 Count Start Flag TA3S RW RW RW RW TA4S TB0S TB1S TB2S 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting Timer A1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer A4 Count Start Flag Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag b6 b5 b3 b2 b1 b4 b7 b0 Figure 15.6 TB2, TRGSR and TABSR Registers |
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