 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
M32C83T Datasheet(PDF) 208 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
M32C83T Datasheet(HTML) 208 Page - Renesas Technology Corp |
|
|
208 / 527 page  Page 185 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 16. Serial I/O (Clock Synchronous Serial I/O) ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Tc TCLK Pulse stops because TE bit = 0 Data is set in the UiTB register Transfer Clock TE bit in UiC1 register TI bit in UiC1 register CLKi TxDi TXEPT bit in UiC0 register "H" "L" CTSi IR bit in SiTIC register "0" "1" Pulse stops because CTSi = H Data is transferred from the UiTB register to the UARTi transmit register Set to "0" by an interrupt request acknowledgement or by program TC=2(m+1)/fj fj : Count source frequency set in the UiBRG register (f1, f8, f2n(1)) m : Setting value of the UiBRG register i = 0 to 4 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division ( n=0) or divide-by-2n (n=1 to 15). The above applies to the following settings: • The CKDIR bit in the UiMR register is set to "0" (internal clock selected) • The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled) The CRS bit is set to "0" (CTS function selected) • The CKPOL bit the in UiC0 register is set to "0" (data transmitted on the falling edge of the transfer clock) • The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register) (1) Transmit Timing (Internal clock selected) "0" "1" "0" "1" "0" "1" Dummy data is set in the UiTB register TE bit in UiC1 register TI bit in UiC1 register CLKi RxDi RI bit in UiC1 register RTSi RE bit in UiC1 register Received data is taken in Data is transferred from the UiTB register to the UARTi transmit register Read by the UiRB register The above applies to the following settings: • The CKDIR bit in the UiMR register is set to "1" (external clock selected) • The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled) The CRS bit is set to "1" (RTS function selected) • The CKPOL bit in the UiC0 register is set to "0" (Data is received on the rising edge of the transfer clock) IR bit in SiRIC register Set to "0" by an interrupt request acknowledgement or by program 1 / fEXT D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5 D7 D6 OER bit in UiRB register D6 Meet the following conditions while "H" is applied to the CLKi pin before receiving data: • Set the TE bit in the UiC1 register to "1" (transmit enable) • Set the RE bit in the UiC1 register to "1" (receive enable) • Write dummy data to the UiTB register fEXT: External clock frequency i=0 to 4 (2) Receive Timing (External clock selected) "H" "L" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" Becomes "L" when the UiRB register is read Data transferred from UARTi register to UiRB register Figure 16.10 Transmit and Receive Operation |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
