M32C83T datasheet(209/527 Pages) RENESAS

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Page 186

16. Serial I/O (Clock Synchronous Serial I/O)

)

(

TXDi

RXDi

CLKi

(1) When the CKPOL bit in the UiC0 register (i=0 to 4) is set to "0"

(Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge)

TXDi

RXDi

CLKi

(2) When the CKPOL bit in the UiC0 register is set to "1"

(Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge)

NOTES:

1. The CLKi pin is held high ("H") when no data is transferred.

2. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)

and the UiLCH bit in the UiC1 register is set to "0" (not inversed).

NOTES:

3. The CLKi pin is held low ("L") when no data is transferred.

4. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)

and the UiLCH bit in the UiC1 register is set to "0" (not inversed).

(1) When the UFORM bit in the UiC0 register (i=0 to 4) is set to "0"

(LSB first)

TXDi

RXDi

CLKi

TXDi

RXDi

CLKi

(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)

NOTES:

2. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is

transmitted on the falling edge of the transfer clock and received on the rising

edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).

NOTES:

1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is

transmitted on the falling edge of the transfer clock and received on the rising

edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).

16.1.1 Selecting CLK Polarity

As shown in Figure 16.11, the CKPOL bit in the UiC0 register (i=0 to 4) determines the polarity of the

transfer clock.

Figure 16.11 Transfer Clock Polarity

16.1.2 Selecting LSB First or MSB First

As shown in Figure 16.12, the UFORM bit in the UiC0 register (i=0 to 4) determines a data transfer format.

Figure 16.12 Transfer Format

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