M32C83T datasheet(216/527 Pages) RENESAS

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Page 193

16. Serial I/O (UART)

)

(

ST : Start bit

P : Parity bit

SP : Stop bit

CLKi

TxDi

RxDi

(1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first)

(2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first)

CLKi

TxDi

RxDi

NOTES:

1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is

transmitted on the falling edge of the transfer clock and received on the rising edge)

and the UiLCH bit in the UiC1 register is set to "0" (no inverse).

16.2.2 Selecting LSB First or MSB First

As shown in Figure 16.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format.

This function is available for 8-bit transfer data.

Figure 16.16 Transfer Format

16.2.3 Serial Data Logic Inverse

After the UiLCH bit in the UiC1 register is set to "1", data logic is inversed when writing to the UiTB register

(i=0 to 4) and reading from the UiRB register. Figure 16.17 shows a switching example of the serial data

logic.

TxDi

(no inverse)

Transfer Clock

“H”

“L”

“H”

“L”

(1) When the UiLCH bit in the UiC1 register (i=0 to 4) = 0 (no inverse)

TxDi

(inverse)

“H”

“L”

Transfer Clock

“H”

“L”

(2) When the UiLCH bit in the UiC1 register = 1 (inverse)

NOTES:

1. The above applies to when the UFORM bit in the UiC0 register is set to "0" (LSB first),

the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled).

Figure 16.17 Serial Data Logic Inverse

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