M32C83T datasheet(259/527 Pages) RENESAS

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17. A/D Converter

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17.1.5 Repeat Sweep Mode 1

In repeat sweep mode 1, analog voltage selectively applied to eight pins is repeatedly converted to a

digital code. Table 17.8 lists specifications of repeat sweep mode 1.

Table 17.8 Repeat Sweep Mode 1 Specifications

Item

Specification

Function

Analog voltage selectively applied to 8 pins selected by the SCAN1 to SCAN0 bits

in the ADiCON1 register (i=0,1) is repeatedly converted to a digital code.

e.g., When ANj0 is selected (j =none, 0, 2, 15), analog voltage is converted to a

digital code in the following order:

ANj0

ANj1

ANj0

ANij2

ANj0

ANj3 ....... etc.

Start Condition

Same as one-shot mode

Stop Condition

The ADST bit in the ADiCON1 register is set to "0" (A/D conversion stopped) by

program

Interrupt Request Generation Timing Not generated

Analog Voltage Input Pins

ANj0 to ANj7 (8 pins)

Prioritized Pins

Select from AN0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), or AN0 to AN3 (4

pins)

Select from ANj0 (j=0, 2, 15) (1 pin), ANj0 to ANj1 (2 pins), AN0 to AN2 (3 pins),

ANj0 to ANj3 (4 pins)

Reading of A/D Conversion Result The ADik register (k=0 to 7) corresponding to selected pins

17.2 Function

17.2.1 Resolution Select Function

The BITS bit in the ADiCON1 (i=0, 1) register determines the resolution. When the BITS bit is set to "1"

(10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the ADij register (j = 0 to 7). When

the BITS bit is set to "0" (8-bit precision), the A/D conversion result is stored into bits 0 to 7 in the ADij

17.2.2 Sample and Hold

When the SMP bit in the ADiCON2 register is set to "1" (with the sample and hold function), A/D conver-

sion rate per pin increases to 28 ØAD cycles for 8-bit resolution and 33 ØAD cycles for 10-bit resolution.

The sample and hold function is available in all operating modes. Start the A/D conversion after selecting

whether the sample and hold function is to be used or not.

17.2.3 Trigger Select Function

The TRG bit in the ADiCON0 register and the TRG1 to TRG0 bits in the ADiCON2 register determine the

trigger to start the A/D conversion. Table 17.9 lists settings of the trigger select function.

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