HD64F3672 datasheet(13/332 Pages) RENESAS

13 / 332 page

Rev.4.00 Nov. 02, 2005 Page xiii of xxiv

11.3.7 Timer Counter (TCNT)......................................................................................... 141

11.3.8 General Registers A to D (GRA to GRD)............................................................. 141

11.4

Operation ........................................................................................................................... 142

11.4.1 Normal Operation ................................................................................................. 142

11.4.2 PWM Operation.................................................................................................... 146

11.5

Operation Timing............................................................................................................... 151

11.5.1 TCNT Count Timing ............................................................................................ 151

11.5.2 Output Compare Output Timing ........................................................................... 151

11.5.3 Input Capture Timing............................................................................................ 152

11.5.4 Timing of Counter Clearing by Compare Match .................................................. 153

11.5.5 Buffer Operation Timing ...................................................................................... 153

11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match.................................. 154

11.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................. 155

11.5.8 Timing of Status Flag Clearing............................................................................. 155

11.6

Usage Notes ....................................................................................................................... 156

Section 12 Watchdog Timer ..............................................................................159

12.1

Features.............................................................................................................................. 159

12.2

Register Descriptions ......................................................................................................... 159

12.2.1 Timer Control/Status Register WD (TCSRWD)................................................... 160

12.2.2 Timer Counter WD (TCWD)................................................................................ 161

12.2.3 Timer Mode Register WD (TMWD) .................................................................... 161

12.3

Operation ........................................................................................................................... 162

Section 13 Serial Communication Interface 3 (SCI3) .......................................163

13.1

Features.............................................................................................................................. 163

13.2

Input/Output Pins ...............................................................................................................165

13.3

Register Descriptions ......................................................................................................... 165

13.3.1 Receive Shift Register (RSR) ............................................................................... 166

13.3.2 Receive Data Register (RDR) ............................................................................... 166

13.3.3 Transmit Shift Register (TSR) .............................................................................. 166

13.3.4 Transmit Data Register (TDR).............................................................................. 166

13.3.5 Serial Mode Register (SMR) ................................................................................ 167

13.3.6 Serial Control Register 3 (SCR3).......................................................................... 168

13.3.7 Serial Status Register (SSR) ................................................................................. 170

13.3.8 Bit Rate Register (BRR) ....................................................................................... 172

13.4

Operation in Asynchronous Mode ..................................................................................... 177

13.4.1 Clock..................................................................................................................... 177

13.4.2 SCI3 Initialization................................................................................................. 178

13.4.3 Data Transmission ................................................................................................ 179

HD64F3672 Datasheet(PDF) 13 Page - Renesas Technology Corp

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