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HD64F36077G Datasheet(PDF) 33 Page - Renesas Technology Corp |
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HD64F36077G Datasheet(HTML) 33 Page - Renesas Technology Corp |
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33 / 564 page ![]() Section 1 Overview Rev. 3.00 Sep. 10, 2007 Page 1 of 528 REJ09B0216-0300 Section 1 Overview 1.1 Features • High-speed H8/300H CPU with an internal 16-bit architecture Upwardly compatible with H8/300 CPU at the object level Sixteen 16-bit general registers 62 basic instructions • Various peripheral functions RTC (can be used as a free running counter) Timer B1 (8-bit timer) Timer V (8-bit timer) Timer Z (16-bit timer) 14-bit PWM Watchdog timer SCI (asynchronous or clock synchronous serial communication interface) × 2 channels I2C bus interface (conforms to the I2C bus interface format that is advocated by Philips Electronics) 10-bit A/D converter POR/LVD (power-on reset & low-voltage detection circuit) On-chip oscillator |
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