M32CSLASH8B datasheet(81/406 Pages) RENESAS

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Under development

M32C/8B Group

8. Bus

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 64 of 385

Figure 8.14

External Bus Timing with Page Mode Control Function

FFF00Ch

FFF008h

FFF001h

FFF000h

3 φ + 3 φ

CS0 (CE)

1 φ + 2 φ

BCLK

Address

Data

RD (OE)

FFF002h

1 φ + 2 φ

FFF007h

1 φ + 2 φ

FFF008h

3 φ + 3 φ

FFF009h

1 φ + 2 φ

The maximum of seven bytes of consective addresses can be read in the page mode control (The total of eight bytes

adding the first bus access). If the MCU accesses data in other than the eight-byte block of consecutive addresses, the

page mode controlled access is started over from the first bus access.

Set using bits PWCR106 to PWCR104

Set using bits EWCR34 to EWCR30

The above applies under the following conditions:

- Bits PM11 and PM10 in the PM1 register are set to 11b (mode 3).

- The DS3 bit in the DS regiter is set to 0 (8 bits wide).

- Bits EWCR34 to EWCR30 in the EWCR3 register are set to 10011b (3 φ + 3 φ).

- The EWCR36 bit is set to 0 (add no recovery cycle when accessing external space 3).

- Bits PWCR106 to PWCR104 are set to 010b (1 φ + 2 φ).

- The PWCR107 bit is set to 1 (page mode control enabled).

FFF002h

FFF000h

3 φ + 3 φ

CS0 (CE)

1 φ + 2 φ

BCLK

Address

Data

RD (OE)

FFF004h

1 φ + 2 φ

FFF006h

3 φ + 3 φ

FFF00Ah

1 φ + 2 φ

The above applies under the following conditions:

- Bits PM11 and PM10 in the PM1 register are set to 11b (mode 3).

- The DS3 bit in the DS regiter is set to 1 (16 bits wide).

- Bits EWCR34 to EWCR30 in the EWCR3 register are set to 10011b (3 φ + 3 φ).

- The EWCR36 bit is set to 0 (add no recovery cycle when accessing external space 3).

- Bits PWCR106 to PWCR104 are set to 010b (1 φ + 2 φ).

- The PWCR107 bit is set to 1 (page mode control enabled).

1 φ + 2 φ

Set using bits PWCR106 to PWCR104

Set using bits EWCR34 to EWCR30

8-bit data bus width

16-bit data bus width

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