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H8S2153 Datasheet(PDF) 29 Page - Renesas Technology Corp |
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H8S2153 Datasheet(HTML) 29 Page - Renesas Technology Corp |
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29 / 750 page  Rev. 2.00 Sep.11, 2008 Page xxix of xxxvi Figure 19.6 System Configuration in Boot Mode....................................................................... 539 Figure 19.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 540 Figure 19.8 Overview of Boot Mode State Transition Diagram................................................. 542 Figure 19.9 Programming/Erasing Overview Flow.................................................................... 543 Figure 19.10 RAM Map When Programming/Erasing is Executed............................................ 544 Figure 19.11 Programming Procedure........................................................................................ 545 Figure 19.12 Erasing Procedure.................................................................................................. 550 Figure 19.13 Repeating Procedure of Erasing and Programming............................................... 552 Figure 19.14 Procedure for Programming User MAT in User Boot Mode ................................ 555 Figure 19.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 557 Figure 19.16 Transitions to Error-Protection State..................................................................... 572 Figure 19.17 Switching between the User MAT and User Boot MAT....................................... 573 Figure 19.18 Boot Program States .............................................................................................. 576 Figure 19.19 Bit-Rate-Adjustment Sequence ............................................................................. 577 Figure 19.20 Communication Protocol Format .......................................................................... 578 Figure 19.21 New Bit-Rate Selection Sequence......................................................................... 589 Figure 19.22 Programming Sequence......................................................................................... 593 Figure 19.23 Erasure Sequence .................................................................................................. 596 Section 20 Boundary Scan (JTAG) Figure 20.1 JTAG Block Diagram.............................................................................................. 606 Figure 20.2 TAP Controller State Transitions ............................................................................ 617 Figure 20.3 Reset Signal Circuit Without Reset Signal Interference.......................................... 621 Figure 20.4 Serial Data Input/Output (1).................................................................................... 622 Figure 20.5 Serial Data Input/Output (2).................................................................................... 623 Section 21 Clock Pulse Generator Figure 21.1 Block Diagram of Clock Pulse Generator ............................................................... 625 Figure 21.2 Typical Connection to Crystal Resonator................................................................ 626 Figure 21.3 Equivalent Circuit of Crystal Resonator.................................................................. 626 Figure 21.4 Example of External Clock Input ............................................................................ 627 Figure 21.5 Note on Board Design of Oscillation Circuit Section............................................... 629 Section 22 Power-Down Modes Figure 22.1 Mode Transition Diagram ....................................................................................... 639 Figure 22.2 Medium-Speed Mode Timing ................................................................................. 642 Figure 22.3 Software Standby Mode Application Example ....................................................... 644 Figure 22.4 Hardware Standby Mode Timing ............................................................................ 645 Section 24 Electrical Characteristics Figure 24.1 Darlington Transistor Drive Circuit (Example)....................................................... 677 Figure 24.2 LED Drive Circuit (Example) ................................................................................. 678 |
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