HD6432142 datasheet(661/1177 Pages) RENESAS

661 / 1177 page

Section 20 A/D Converter

Rev. 4.00 Sep 27, 2006 page 617 of 1130

REJ09B0327-0400

The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected

channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte

(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and

stored. Bits 5 to 0 are always read as 0.

The correspondence between the analog input channels and ADDR registers is shown in table

20.3.

The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for

the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section

20.3, Interface to Bus Master.

The ADDR registers are initialized to H'0000 by a reset, and in standby mode, watch mode,

subactive mode, subsleep mode, and module stop mode.

Table 20.3

Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel

Group 0

Group 1

A/D Data Register

AN0

AN4

ADDRA

AN1

AN5

ADDRB

AN2

AN6 or CIN0 to CIN7

ADDRC

AN3

AN7 or CIN8 to CIN15

ADDRD

20.2.2

A/D Control/Status Register (ADCSR)

ADF

R/(W)*

ADIE

R/W

ADST

R/W

SCAN

R/W

CKS

R/W

CH0

R/W

CH2

R/W

CH1

R/W

Bit

Initial value

Read/Write

Note: * Only 0 can be written in bit 7, to clear the flag.

ADCSR is an 8-bit readable/writable register that controls A/D conversion operations.

ADCSR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,

subsleep mode, and module stop mode.

HD6432142 Datasheet(PDF) 661 Page - Renesas Technology Corp

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