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HD6432142 Datasheet(PDF) 744 Page - Renesas Technology Corp |
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HD6432142 Datasheet(HTML) 744 Page - Renesas Technology Corp |
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744 / 1177 page ![]() Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version) Rev. 4.00 Sep 27, 2006 page 700 of 1130 REJ09B0327-0400 Table 23.5 Flash Memory Erase Blocks Block (Size) 128-kbyte Version 64-kbyte Version Address EB0 (1 kbyte) EB0 (1 kbyte) H'(00)0000 to H'(00)03FF EB1 (1 kbyte) EB1 (1 kbyte) H'(00)0400 to H'(00)07FF EB2 (1 kbyte) EB2 (1 kbyte) H'(00)0800 to H'(00)0BFF EB3 (1 kbytes) EB3 (1 kbytes) H'(00)0C00 to H'(00)0FFF EB4 (28 kbytes) EB4 (28 kbytes) H'(00)1000 to H'(00)7FFF EB5 (16 kbytes) EB5 (16 kbytes) H'(00)8000 to H'(00)BFFF EB6 (8 kbytes) EB6 (8 kbytes) H'(00)C000 to H'(00)DFFF EB7 (8 kbytes) EB7 (8 kbytes) H'00E000 to H'00FFFF EB8 (32 kbytes) — H'010000 to H'017FFF EB9 (32 kbytes) — H'018000 to H'01FFFF 23.5.4 Serial/Timer Control Register (STCR) Bit 7 6 543210 IICS IICX1 IICX0 IICE FLSHE — ICKS1 ICKS0 Initial value 0 0 000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode (when the on-chip IIC option is included), and on-chip flash memory, and also selects the TCNT input clock. For details on functions not related to on-chip flash memory, see section 3.2.4, Serial/Timer Control Register (STCR), and descriptions of individual modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4—I 2C Control (IICS, IICX1, IICX0, IICE): These bits control the operation of the I2C bus interface for the I 2C on-chip option. For details, see section 16, I2C Bus Interface. |
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