HD6432142 datasheet(922/1177 Pages) RENESAS

922 / 1177 page

Section 26 Electrical Characteristics

Rev. 4.00 Sep 27, 2006 page 878 of 1130

REJ09B0327-0400

(3) Bus Timing

Table 26.50 shows the bus timing. Operation in external expansion mode is not guaranteed when

operating on the subclock (

φ = 32.768 kHz).

Table 26.50 Bus Timing

Condition A: V

CC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency,

a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range

specifications)

Condition B: V

CC = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency,

a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range

specifications)

Condition C: V

CC = 2.7 V to 5.5 V (mask ROM version), VCC = 3.0 V to 5.5 V (F-ZTAT version),

SS = 0 V, φ = 2 MHz to maximum operating frequency,

a = –20 to +75°C

Condition A

Condition B

Condition C

20 MHz

16 MHz

10 MHz

Item

Symbol Min

Max

Min

Max

Min

Max

Unit

Test

Conditions

Address

delay time

—20

—

Address

setup time

0.5

cyc –15

—0.5

cyc –20

—0.5

cyc –30

—ns

Figure 26.10

figure 26.14

Address

hold time

0.5

cyc –10

—0.5

cyc –15

—0.5

cyc –20

—ns

CS delay

time (

IOS)

CSD

—20

—

AS delay

time

ASD

—30

—

RD delay

time 1

RSD1

—30

—

RD delay

time 2

RSD2

—30

—

Read data

setup time

RDS

—

Read data

hold time

RDH

0—

—

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