HD64F3039F datasheet(73/708 Pages) RENESAS

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Section 2 CPU

Rev.3.00 Mar. 26, 2007 Page 51 of 682

REJ09B0353-0300

Exception

sources

Reset

Interrupt

Trap instruction

External interrupts

Internal interrupts (from on-chip supporting modules)

Figure 2.12 Classification of Exception Sources

Exception-handling state

Program execution state

Sleep mode

Software standby mode

Power-down state

End of

exception

handling

Exception

Interrupt

SLEEP

instruction

with SSBY = 0

SLEEP instruction

with SSBY = 1

NMI, IRQ , IRQ ,

or IRQ interrupt

STBY = high, RES = low

RES = high

Notes: 1.

From any state except hardware standby mode, a transition to the reset state occurs

whenever

goes low.

From any state, a transition to hardware standby mode occurs when

goes low.

RES

STBY

Hardware standby mode*2

Reset state*1

Figure 2.13 State Transitions

2.8.4

Exception-Handling Sequences

Reset Exception Handling: Reset exception handling has the highest priority. The reset state is

entered when the

RES signal goes low. Reset exception handling starts after that, when RES

changes from low to high. When reset exception handling starts the CPU fetches a start address

from the exception vector table and starts program execution from that address. All interrupts,

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