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HD6433020F Datasheet(PDF) 9 Page - Renesas Technology Corp |
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HD6433020F Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 712 page ![]() Rev.2.00 Mar. 22, 2007 Page ix of xxiv REJ09B0352-0200 Item Page Revision (See Manual for Details) 11.2.8 Bit Rate Register (BRR) 350 Description amended The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby mode. The baud rate generator is controlled separately for the individual channels, so different values may be set for each. Table 11.3 shows examples of BRR settings in asynchronous mode. Table 11.4 shows examples of BRR settings in synchronous mode. Table 11.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode 352 Table amended φφ (MHz) 6 Bit Rate (bits/s) n N Error ( %) 110 2 106 –0.44 150 2 77 0.16 300 1 155 0.16 12 n N Error ( %) 2 212 0.03 2 155 0.16 2 77 0.16 11.3.4 Synchronous Operation Figure 11.17 Example of SCI Transmit Operation 382 Figure amended Transmit direction Serial clock Serial data TDRE TEND Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TXI interrupt handler writes data in TDR and clears TDRE flag to 0 TXI request TXI request TEI request 1 frame 15.8.3 Error Protection Figure 15.13 Flash Memory State Transitions (Modes 5, 6, and 7 (on-chip ROM enabled), high level applied to FWE pin) 485 Figure amended RD VF PR ER INIT FLER= 1 Error protection mode (software standby) 16.2.1 Connecting a Crystal Resonator Table 16.2 Crystal Resonator Parameters 504 Preliminary deleted |
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