HD6433723 datasheet(13/352 Pages) RENESAS

13 / 352 page

Rev. 3.00, 12/94, page xii of xiv

10.3.5 SCI1 State Transitions ........................................................................................ 202

10.3.6 Transfer Clock Error Detection .......................................................................... 203

10.3.7 Interrupts............................................................................................................. 204

Section 11 SCI2 .................................................................................................................. 205

11.1

Overview......................................................................................................................... 205

11.1.1 Features............................................................................................................... 205

11.1.2 Block Diagram.................................................................................................... 205

11.1.3 Pin Configuration................................................................................................ 206

11.1.4 Register Configuration........................................................................................ 206

11.2

Register Descriptions...................................................................................................... 207

11.2.1 Start Address Register (STAR)........................................................................... 207

11.2.2 End Address Register (EDAR) ........................................................................... 207

11.2.3 Serial Control Register 2 (SCR2) ....................................................................... 208

11.2.4 Status Register (STSR) ....................................................................................... 209

11.2.5 Port Mode Register 3 (PMR3) ............................................................................ 211

11.3

Operation ........................................................................................................................ 213

11.3.1 Overview............................................................................................................. 213

11.3.2 Clock................................................................................................................... 214

11.3.3 Data Transfer Format.......................................................................................... 214

11.3.4 Data Transmit/Receive........................................................................................ 216

11.4

Interrupts......................................................................................................................... 218

11.5

Application Notes ........................................................................................................... 218

Section 12 VFD Controller/Driver ................................................................................ 219

12.1

Overview......................................................................................................................... 219

12.1.1 Features............................................................................................................... 219

12.1.2 Block Diagram.................................................................................................... 219

12.1.3 Pin Configuration................................................................................................ 220

12.1.4 Register Configuration........................................................................................ 220

12.2

Register Descriptions...................................................................................................... 221

12.2.1 VFD Digital Control Register (VFDR) .............................................................. 221

12.2.2 VFD Segment Control Register (VFSR) ............................................................ 224

12.2.3 Digit Beginning Register (DBR) ........................................................................ 226

12.3

Operation ........................................................................................................................ 228

12.3.1 Overview............................................................................................................. 228

12.3.2 Control Part......................................................................................................... 228

12.3.3 RAM Bit Correspondence to Digits/Segments................................................... 228

12.3.4 Procedure for Starting Operation........................................................................ 230

12.4

Interrupts......................................................................................................................... 230

12.5

Occurrence of Flicker when the VFD Register Is Rewritten .......................................... 230

HD6433723 Datasheet(PDF) 13 Page - Renesas Technology Corp

HD6433723 Datasheet(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL