SH7055S datasheet(39/1002 Pages) RENESAS

39 / 1002 page

Rev.2.0, 07/03, page 1 of 960

Section 1 Overview

1.1

Features

The SH7055SF is a single-chip RISC microcontroller that integrates a RISC CPU core using an

original Renesas architecture with peripheral functions required for system configuration.

The CPU has a RISC-type instruction set. Basic instructions can be executed in one state (one

system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit

internal architecture enhances data processing power. With this CPU, it has become possible to

assemble low-cost, high-performance/high-functionality systems even for applications such as

real-time control, which could not previously be handled by microcontrollers because of their

high-speed processing requirements.

In addition, the SH7055SF includes on-chip peripheral functions necessary for system

configuration, such as a floating-point unit (FPU) , ROM , RAM, a direct memory access

controller (DMAC), timers, a serial communication interface (SCI), controller area network

(HCAN), A/D converter, interrupt controller (INTC), and I/O ports.

ROM and SRAM can be directly connected by means of an external memory access support

function, greatly reducing system cost.

On-chip ROM is available as flash memory in the F-ZTAT™* (Flexible Zero Turn Around Time)

version. The flash memory can be programmed with a programmer that supports SH7055SF

programming, and can also be programmed and erased by software. Since the

programming/erasing control program is included as firmware, programming and erasing can be

performed by calling this program with a user program. This enables the chip to be programmed at

the user site while mounted on a board.

The features of the SH7055SF are summarized in table 1.1.

Note

: * F-ZTAT is a trademark of Renesas Technology Corp.

SH7055S Datasheet(PDF) 39 Page - Renesas Technology Corp