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HD64F7055S Datasheet(PDF) 9 Page - Renesas Technology Corp |
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HD64F7055S Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 1002 page  Rev.2.0, 07/03, page ix of xxxviii Item Page Revisions (See Manual for Details) 11.1.1 Features 191 to 193 Description amended Prescaler 1/1 to 1/32 clock scaling possible in initial stage for channels 0 to 8, 10, and 11 Channels 1 to 5 enable TI10 pin input, multiple the TI10 pin input (correction), and select AGCK and AGCKM. Channel 2 Provision for forcible cutoff of channel 8 down- counters(DCNT8I to P) Channel 8 Reload function can be set to eight 16-bit down counters (DCNT8I to DCNT8P) Channel 9 • Channel 9 has six event counters and six general registers, allowing the following operations: Channel 10 • Channel 10 has a 32-bit output compare and input capture register, free-running counter, 16-bit free- running counter, output compare/input capture register, reload register, 8-bit event counter, and output compare register, and one 16-bit reload counter, allowing the following operations: Reload count possible with 1/32, 1/64, 1/128, or 1/256 times the captured value Channel 11 Waveform output at compare match: 0 output, 1 output, and toggle output selectable Input capture function: Detection at rising edge, falling edge, and both edges Compare-match signal can be output at the APC by using a general register as a output compare register |
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