| Electronic Components Datasheet Search |
|
SH7058F Datasheet(PDF) 13 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7058F Datasheet(HTML) 13 Page - Renesas Technology Corp |
|
13 / 1130 page ![]() Rev. 3.0, 09/04, page x of xxxviii Item Page Revisions (See Manual for Details) 16.3.2 Message Control Field 530- 532 Table amended Register Name Address Bit Bit Name Description MBx[4], MBx[5]* H'104 + N x 32 15 CCM CAN-ID Compare Match When this bit is set, message reception in the corresponding mailbox can generate two triggers. If TCR9 is set to 1, TCR14 is cleared to freeze ICR0. If TCR10 is set to 1, TCNTR (timer counter register) is automatically cleared and the LOSR (local offset register) value is set. Important: This function is not supported by the SH7058. Thus the write value should be 0. 14 TTE Time Trigger Enable When this bit is set, a mailbox in which TXPR has been already set transmits a message at a time set in the Tx trigger time field. Important: If this bit is set, a failure occurs during message transmission. Therefore setting is prohibited. The write value should be 0. The value read as the initial value is not guaranteed. MBx[4], MBx[5]* H'104 + N x 32 13 NMC New Message Control When this bit is cleared, a mailbox in which PXPR/PFPR has been already set does not store the new message but retains the previous one and sets the UMSR corresponding bit. When this bit is set, a mailbox in which PXPR/PFPR has been already set stores the new message and sets the UMSR corresponding bit. If a message is received in a mailbox in overwrite mode (NMC = 1), the host CPU must perform an additional check at the end of the data reading from the mailbox in order to guarantee that the mailbox data have not been corrupted during such operation by another receive message. The additional check, to be performed at the end of the mailbox access, consists in verifying that the associated bit of UMSR has not been set and so no overwrite has occurred; in case such bit is set data have been corrupted and so the message must be discarded. MBx[4], MBx[5]* H'104 + N x 32 11 DART Disable Automatic Retransmission When this bit is set, it disables the automatic retransmission of a message in the event of an error on the CAN bus or an arbitration lost on the CAN bus. When this function is used, the corresponding TXCR bit is automatically set at the start of transmission. When this bit is cleared, the HCAN tries to transmit the message as many times as required until it is successfully transmitted or it is cancelled by the TXCR. Important: This function is not supported by the SH7058. Thus the write value should be 0. The value read as the initial value is not guaranteed. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |