M16CSLASH62 datasheet(94/615 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

1-75

Single-chip mode

Memory expansion mode

Transfer unit

Bus width

Access address

Microprocessor mode

No. of read

No. of write

No. of read No. of write

cycles

16-bit

Even

1111

8-bit transfers

(BYTE= “L”)

Odd

1111

(DMBIT= “1”)

8-bit

Even

—

(BYTE = “H”)

Odd

—

16-bit

Even

1111

16-bit transfers

(BYTE = “L”)

Odd

2222

(DMBIT= “0”)

8-bit

Even

—

(BYTE = “H”)

Odd

—

Table 1.13.2. No. of DMAC transfer cycles

Internal memory

External memory

Internal ROM/RAM

SFR area

Separate bus

Multiplex

No wait

With wait

No wait

With wait

bus

Coefficient j, k

(2) DMAC transfer cycles

Any combination of even or odd transfer read and write addresses is possible. Table 1.13.2 shows the

number of DMAC transfer cycles.

The number of DMAC transfer cycles can be calculated as follows:

No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k

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