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SH7712 Datasheet(PDF) 22 Page - Renesas Technology Corp |
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SH7712 Datasheet(HTML) 22 Page - Renesas Technology Corp |
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22 / 978 page  Rev. 1.00 Dec. 27, 2005 Page xxii of xlii 17.5 Usage Notes ....................................................................................................................... 635 Section 18 Ethernet Controller (EtherC) ........................................................... 637 18.1 Features.............................................................................................................................. 637 18.2 Input/Output Pins ...............................................................................................................639 18.3 Register Descriptions ......................................................................................................... 641 18.3.1 Software Reset Register (ARSTR) ....................................................................... 644 18.3.2 EtherC Mode Register (ECMR)............................................................................ 645 18.3.3 EtherC Status Register (ECSR) ............................................................................ 648 18.3.4 EtherC Interrupt Permission Register (ECSIPR) .................................................. 649 18.3.5 PHY Interface Register (PIR) ............................................................................... 650 18.3.6 MAC Address High Register (MAHR) ................................................................ 651 18.3.7 MAC Address Low Register (MALR) ................................................................. 651 18.3.8 Receive Frame Length Register (RFLR) .............................................................. 652 18.3.9 PHY Status Register (PSR)................................................................................... 653 18.3.10 Transmit Retry Over Counter Register (TROCR) ................................................ 653 18.3.11 Delayed Collision Detect Counter Register (CDCR)............................................ 654 18.3.12 Lost Carrier Counter Register (LCCR)................................................................. 654 18.3.13 Carrier Not Detect Counter Register (CNDCR) ................................................... 654 18.3.14 CRC Error Frame Receive Counter Register (CEFCR)........................................ 655 18.3.15 Frame Receive Error Counter Register (FRECR)................................................. 655 18.3.16 Too-Short Frame Receive Counter Register (TSFRCR) ...................................... 655 18.3.17 Too-Long Frame Receive Counter Register (TLFRCR) ...................................... 656 18.3.18 Residual-Bit Frame Receive Counter Register (RFCR) ....................................... 656 18.3.19 Multicast Address Frame Receive Counter Register (MAFCR)........................... 657 18.3.20 IPG Register (IPGR)............................................................................................. 657 18.3.21 TSU Counter Reset Register (TSU_CTRST) ....................................................... 658 18.3.22 Relay Enable Register (Port 0 to 1) (TSU_FWEN0) ............................................ 658 18.3.23 Relay Enable Register (Port 1 to 0) (TSU_FWEN1) ............................................ 659 18.3.24 Relay FIFO Size Select Register (TSU_FCM) ..................................................... 660 18.3.25 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0) ..................... 661 18.3.26 Relay FIFO Overflow Alert Set Register (Port 1) (TSU_BSYSL1) ..................... 662 18.3.27 Transmit/Relay Priority Control Mode Register (Port 0) (TSU_PRISL0)............ 663 18.3.28 Transmit/Relay Priority Control Mode Register (Port 1) (TSU_PRISL1)............ 664 18.3.29 Receive/Relay Function Set Register (Port 0 to 1) (TSU_FWSL0)...................... 666 18.3.30 Receive/Relay Function Set Register (Port 1 to 0) (TSU_FWSL1)...................... 667 18.3.31 Relay Function Set Register (Common) (TSU_FWSLC)..................................... 669 18.3.32 Qtag Addition/Deletion Set Register (Port 0 to 1) (TSU_QTAGM0) .................. 671 18.3.33 Qtag Addition/Deletion Set Register (Port 1 to 0) (TSU_QTAGM1) .................. 672 18.3.34 Relay Status Register (TSU_FWSR) .................................................................... 673 |
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