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7540 Datasheet(PDF) 101 Page - Renesas Technology Corp

Part # 7540
Description  8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 740 SERIES
PDF  366 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7540 Datasheet(HTML) 101 Page - Renesas Technology Corp

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2-25
REJ09B0018-0200Z
Rev.2.00
Jun 21, 2004
7540 Group
APPLICATION
2.2 Timer A
Fig. 2.2.16 Example of control procedure
“FF16”
“FF16”
Set timer A mode register
0
TAM(Address 1D16)
Timer A count start
1
CLI
0
RESET
SEI
CLD
CLT
CPUM (Address 3B16)
← 10000X002
Wait until f(XIN) oscillation is stabilized (Note 1)
CPUM (Address 3B16)
← 00000X002
Processing
Timer A interrupt processing routine
Error processing
RTI
0
TAM(Address 1D16)
Period measurement mode
Rising period measured
Rising edge active for CNTR1
interrupt
Timer A count stop
1
Set timer A mode register
1 1
Set port P00 to the input mode.
PULL(Address 1616)
P00 pull-up control bit
0: Pull-up Off
1: Pull-up On
Set pull-up control register
1
CNTR1 interrupt processing routine
Read timer A (Note 3)
RTI
Error processing at incorrect period input
INTEDGE(Address 3A16)
Key-on wakeup disabled
1
CNTR1 interrupt processing
Timer A interrupt processing
Set “0” to the CNTR1 interrupt enable bit.
(CNTR1 interrupt disabled)
Set “0” to the timer A interrupt enable bit.
(Timer A interrupt disabled)
Initialization
X: This bit is not used here. Set it to “0” or “1” arbitrary.
Notes 1: For the concrete time, ask the oscillator manufacture.
2: When setting the value to timer A, set in order of low-order byte
and high-order byte following.
3: When reading a value of timer A, read in order of high-order byte
and low-order byte following.
Timer A (low-order) (Address 1E16)
Set value to timer A (Note 2)
Timer A (high-order) (Address 1F16)
Set interrupt edge selection register
Set “1” to the CNTR1 interrupt enable bit.
(CNTR1 interrupt enabled)
Set “1” to the timer A interrupt enable bit.
(Timer A interrupt enabled)
Set “0” to the CNTR1 interrupt request bit.
Set “0” to the timer A interrupt request bit.



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