7540 datasheet(178/366 Pages) RENESAS

178 / 366 page

2-102

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

APPLICATION

7540 Group

2.6 Serial I/O1

Fig. 2.6.3 Structure of Serial I/O1 status register

Fig. 2.6.4 Structure of Serial I/O1 control register

Serial I/O1 status register

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Serial I/O1 status register (SIO1STS) [Address : 19 16]

Nothing is allocated for this bit. This is a write disabled bit.

When this bit is read out, the value is “1”.

Transmit buffer empty flag

(TBE)

0 : (OE)

∪ (PE) ∪ (FE) = 0

1 : (OE)

∪ (PE) ∪ (FE) = 1

Overrun error flag (OE)

0 : Buffer full

1 : Buffer empty

Receive buffer full flag (RBF)

Transmit shift register shift

completion flag (TSC)

Parity error flag (PE)

Framing error flag (FE)

Summing error flag (SE)

0 : Buffer empty

1 : Buffer full

0 : Transmit shift in progress

1 : Transmit shift completed

0 : No error

1 : Overrun error

0 : No error

1 : Parity error

0 : No error

1 : Framing error

Serial I/O1 control register

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Serial I/O1 control register (SIO1CON) [Address : 1A 16]

0 : f(XIN)

1 : f(XIN)/4

BRG count source

selection bit (CSS)

0 : Transmit disabled

1 : Transmit enabled

0 : Receive disabled

1 : Receive enabled

Transmit interrupt

source selection bit (TIC)

Transmit enable bit (TE)

Receive enable bit (RE)

Serial I/O1 enable bit

(SIOE)

0 : Interrupt when transmit buffer

has emptied

1 : Interrupt when transmit shift

operation is completed

0: Serial I/O1 disabled

1: Serial I/O1 enabled

Serial I/O1 synchronous clock

selection bit (SCS)

When clock synchronous serial I/O

is selected;

0: BRG output divided by 4

1: External clock input

When UART is selected;

0: BRG output divided by 16

1: External clock input divided by 16

SRDY1 output enable bit

(SRDY)

0: P13 pin

1: SRDY1 output pin

Serial I/O1 mode selection bit

(SIOM)

0: Clock asynchronous (UART)

serial I/O

1: Clock synchronous serial I/O

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