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7540 Datasheet(PDF) 179 Page - Renesas Technology Corp |
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7540 Datasheet(HTML) 179 Page - Renesas Technology Corp |
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179 / 366 page ![]() 2-103 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 7540 Group APPLICATION 2.6 Serial I/O1 Fig. 2.6.5 Structure of UART control register Fig. 2.6.6 Structure of Baud rate generator b7b6b5b4b3b2b1b0 B Function At reset RW 0 1 2 3 4 5 6 7 Name 0 0 0 0 1 UART control register (UARTCON) [Address : 1B16] Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “1”. ✕ ✕ ✕ UART control register Character length selection bit (CHAS) Parity enable bit (PARE) Stop bit length selection bit (STPS) Parity selection bit (PARS) In output mode 0 : CMOS output 1 : N-channel open-drain output 0 : 8 bits 1 : 7 bits 0 : Parity checking disabled 1 : Parity checking enabled 0 : 1 stop bit 1 : 2 stop bits 0 : Even parity 1 : Odd parity P11/TxD P-channel output disable bit (POFF) 1 1 0 Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 B Function At reset RW 0 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Baud rate generator (BRG) [Address : 1C 16] Set a count value of baud rate generator. |
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