7540 datasheet(183/366 Pages) RENESAS

183 / 366 page

2-107

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

7540 Group

APPLICATION

2.6 Serial I/O1

Fig. 2.6.10 Setting method for clock synchronous serial I/O1 (1)

Interrupt control register 1 (ICON1) [Address 3E16]

b7b0

Serial I/O1 receive interrupt disabled

Serial I/O1 transmit interrupt disabled

Baud rate generator (BRG) [Address 1C16]

Set baud rate value

b7b0

0 0

Process 1: Stop and initialize serial I/O.

Serial I/O1 control register (SIO1CON) [Address 1A16]

Transmit operation stop and initialized

Receive operation stop and initialized

BRG count source selected (set in internal clock selected)

0: f(XIN)

1: f(XIN)/4

Serial I/O1 synchronous clock selected

0: BRG output/4 (Note 1)

1: External clock input

SRDY1 output enable selected

0: P13 pin operates as normal I/O pin

1: P13 pin operates as SRDY1 output pin (Note 2)

Transmit interrupt source selected

0: When transmit buffer has emptied

1: When transmit shift operation is completed

Transmit enable selected

0: Transmit disabled (at half-duplex communication receive)

1: Transmit enabled (at full-duplex communication) (Note 3)

Receive enable selected

0: Receive disabled (at half-duplex communication transmit)

1: Receive enabled (at full-duplex communication) (Note 3)

Clock synchronous serial I/O

Serial I/O1 enabled

(P10–P13 pins operate as serial I/O1 pins)

Serial I/O1 control register (SIO1CON) [Address 1A16]

Process 3: Set serial I/O1 control register.

1 1

Notes 1: Setting of serial I/O1 synchronous selection bit is as follows:

“0”: P12

pin is set to be an output pin of the synchronous clock.

“1”: P12 pin is set to be an input pin of the synchronous clock.

2: When an external clock input is selected as the synchronous clock, and the receiver

performs the SRDY1 output, set “1” to the transmit enable bit in addition to the receive

enable bit and SRDY1 output enable bit.

3: When data transmission is executed at the state that an external clock input is

selected as the synchronous clock, set “1” to the transmit enable bit while the SCLK1

is “H” state.

Process 2: Disable serial I/O1 transmit/receive interrupt.

Process 4: When BRG output/4 is selected as synchronous clock, set value to baud rate generator.

(2) Clock synchronous serial I/O setting method

Figure 2.6.10 and Figure 2.6.11 show the setting method for the clock synchronous serial I/O1.

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