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7540 Datasheet(PDF) 238 Page - Renesas Technology Corp |
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7540 Datasheet(HTML) 238 Page - Renesas Technology Corp |
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238 / 366 page ![]() 3-16 REJ09B0018-0200Z Rev.2.00 Jun 21, 2004 APPENDIX 7540 Group 3.1 Electrical characteristics (3) Electrical Characteristics (Extended operating temperature version) Table 3.1.16 Electrical characteristics (1) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Min. Typ. Max. Symbol Parameter Limits Unit IOH = –5 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 2.4 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.4 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.4 to 5.5 V VI = VCC (Pin floating. Pull up transistors “off”) VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors “off”) VI = VSS VI = VSS VI = VSS (Pull up transistors “on”) When clock stopped VCC = 5.0 V, Ta = 25 °C VCC = 5.0 V, Ta = 25 °C Test conditions VCC–1.5 VCC–1.0 2.0 1000 62.5 “H” output voltage P00–P07, P10–P14, P20–P27, P30–P37 (Note 1) “L” output voltage P00–P07, P10–P14, P20–P27, P37 “L” output voltage P30–P36 Hysteresis CNTR0, CNTR1, INT0, INT1(Note 2) P00–P07 (Note 3) Hysteresis RXD, SCLK1, SCLK2, SDATA2 (Note 2) Hysteresis RESET “H” input current P00–P07, P10–P14, P20–P27, P30–P37 “H” input current RESET “H” input current XIN “L” input current P00–P07, P10–P14, P20–P27, P30–P37 “L” input current RESET, CNVSS “L” input current XIN “L” input current P00–P07, P30–P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 –5.0 –5.0 –0.5 5.5 3000 187.5 V V V V V V V V V V V µA µA µA µA µA µA mA V kHz kHz VOH VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM ROSC DOSC 0.4 0.5 0.5 4.0 –4.0 –0.2 2000 125 Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level). 3: It is available only when operating key-on wake up. |
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