H83029 datasheet(22/1010 Pages) RENESAS

22 / 1010 page

Rev. 2.0, 06/04, page xix of xxiv

11.4.2 Note on Non-Overlapping Output ....................................................................... 439

Section 12 Watchdog Timer ..............................................................................441

12.1

Overview........................................................................................................................... 441

12.1.1 Features................................................................................................................ 441

12.1.2 Block Diagram ..................................................................................................... 442

12.1.3 Register Configuration......................................................................................... 442

12.2

Register Descriptions ........................................................................................................ 443

12.2.1 Timer Counter (TCNT)........................................................................................ 443

12.2.2 Timer Control/Status Register (TCSR) ................................................................ 444

12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 446

12.2.4 Notes on Register Access..................................................................................... 447

12.3

Operation .......................................................................................................................... 449

12.3.1 Watchdog Timer Operation ................................................................................. 449

12.3.2 Interval Timer Operation ..................................................................................... 450

12.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 451

12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 452

12.4

Interrupts ........................................................................................................................... 453

12.5

Usage Notes ...................................................................................................................... 453

Section 13 Serial Communication Interface ......................................................455

13.1

Overview........................................................................................................................... 455

13.1.1 Features................................................................................................................ 455

13.1.2 Block Diagram ..................................................................................................... 457

13.1.3 Input/Output Pins ................................................................................................. 458

13.1.4 Register Configuration......................................................................................... 459

13.2

Register Descriptions ........................................................................................................ 460

13.2.1 Receive Shift Register (RSR)............................................................................... 460

13.2.2 Receive Data Register (RDR) .............................................................................. 460

13.2.3 Transmit Shift Register (TSR) ............................................................................. 461

13.2.4 Transmit Data Register (TDR)............................................................................. 461

13.2.5 Serial Mode Register (SMR)................................................................................ 462

13.2.6 Serial Control Register (SCR).............................................................................. 466

13.2.7 Serial Status Register (SSR)................................................................................. 471

13.2.8 Bit Rate Register (BRR)....................................................................................... 476

13.3

Operation .......................................................................................................................... 483

13.3.1 Overview.............................................................................................................. 483

13.3.2 Operation in Asynchronous Mode ....................................................................... 485

13.3.3 Multiprocessor Communication........................................................................... 495

13.3.4 Synchronous Operation........................................................................................ 501

13.4

SCI Interrupts.................................................................................................................... 510

13.5

Usage Notes ...................................................................................................................... 510

13.5.1 Notes on Use of SCI ............................................................................................ 510

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