HD6433028F datasheet(13/923 Pages) RENESAS

13 / 923 page

Rev. 2.00, 09/03, page xiii of xxx

Item

Page

Revision (See Manual for Details)

Table 21.5 Control

Signal Timing

653

Conditions amended

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to

AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range

specifications)

Table amended

RESO output delay time

tRESO

—

100

Table 21.6 Bus Timing 654,

655

Conditions amended

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to

AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range

specifications)

Table amended

RAS precharge

time

tRP

1.5 tcyc – 25

—

Figure 21.17 to

figure 21.19

CAS precharge

time

tCP

0.5 tcyc – 15

—

Row address hold

time

tRAH

0.5 tcyc – 15

—

Signal rise time

(all input pins

except EXTAL)

tSR

—

100

Figure 21.28

Signal fall time

(all input pins

except EXTAL)

tSF

—

100

Table 21.7 Timing of

On-Chip Supporting

Modules

656

Conditions amended

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to

AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range

specifications)

HD6433028F Datasheet(PDF) 13 Page - Renesas Technology Corp

HD6433028F Datasheet(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL