S1

RT1

C4

R9

C6

R1

D1

C5

C7

C1

R6

R7

C9

R8

R12

R11

R10

C8

C2

R5

RT2

C11

R3

C3

R4

TDA 1675A

YOKE

GND

SYNC.

IN

Iy

TEST

BLANK

OUT

GND

Figure 6 : PC Board and Components Layout for the Application Circuits of Figures 3, 4 and 5 (1 : 1 scale)

APPLICATION INFORMATION (Refer to the

block diagram)

Oscillator and sync gate (Clock generation)

The oscillator is obtained by means of an integrator

high or low so allowing the charge or the discharge

The Sync input pulse at the Sync gate lowers the

level of the upper threshold and than it controls the

period duration. A clock pulse is generated.

Pin 4

is the inverting input of the amplifier used

as integrator.

Pin 6

is the output of the switch driven by the

internal clock pulse generated by the

threshold circuits.

Pin 3

is the output of the amplifier.

Pin 5

is the input for sync pulses (positive)

Ramp generator and buffer stage

A current mirror, the current intensity of which can

be externally adjusted, charges one capacitor

producing a linear voltage ramp.

The internal clock pulse stops the increasing ramp

by a very fast discharge of the capacitor a new

voltage ramp is immediately allowed.

TDA1675A

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