TDA9110 datasheet(16/29 Pages) STMICROELECTRONICS

16 / 29 page

Of course, when the choice is done, we can refresh

the synchro detectionsand verify that the extracted

Vsync is present and that no synchro type change

have occured.

Synchro processor is also giving synchro polarity

information.

I.7 - IC status

The IC can inform the MCUabout the 1st Horizontal

PLL or Vertical section status (locked or not), and

about the Xray protection (activated or not).

Resettingthe Xray internal latch can be done either

by decreasing the VCC supply or directly resetting

via the I

2C interface.

I.8 - Synchro Inputs

Both H/HVin and Vsyncin inputs are TTL compat-

ible triggers with Hysterisis to avoid erratic detec-

tion. It includes pull up resistor to VDD.

I.9 - Synchro Processor Output

The synchro processor delivers the Hlockout signal

on a TTL-compatible CMOS output.

Hlockout is the Horizontal 1st PLL status (5V when

locked). It allows the MCU to check the Horizontal

IC locking.

II - HORIZONTAL PART

II.1 - Internal Input Conditions

A digital signal (Horizontal synchro pulse or TTL

composite) is sent by the synchro processor to the

horizontal part.

Positive or negative signal can be applied to the

Horizontal part input (see Figure 6).

Using internal integration, both signals are recog-

nized if Z/T < 25%. Synchronization occurs on the

leading edge of the internal synchro signal. The

minimum value of Z is 0.7

µs.

OPERATING DESCRIPTION (continued)

Figure 6

An other integration is able to extract vertical pulse

of composite synchro if duty cycle is higher than

25% (typically d = 35%) (see Figure 7).

TRAMEXT

Figure 7

The last feature performed is the removing of

equalizing pulses to avoid parasitic pulses on

phase comparator input (which is sensitive to

wrong or missing pulses).

II.2 - PLL1

The PLL1 consists of a phase comparator, an exter-

nal filter and a voltage control oscillator (VCO).

The phase comparator is a ”phase frequency” type

designed in CMOS technology. This kind of phase

detector avoids locking on false frequencies. It is

followed by a ”charge pump”, composed of two

current sources sunk and sourced(Typically I = 1mA

when locked and I = 140

µA when unlocked). This

difference between lock/unlock permits a smooth

catching of the horizontal frequency by the PLL1.

This effect is reinforced by an internal original slow

down system when the PLL1 is locked, avoiding the

Horizontal frequency to change too fast.

The dynamic behaviour of the PLL1 is fixed by an

external filter which integrates the current of the

charge pump. A ”CRC” filter is generally used (see

Figure 8).

PLL1F

Figure 8

ThePLL1is internallyinhibitedduringextractedvertical

synchro (if any) to avoid taking in account missing

pulses or wrong pulses on phase comparator.The

inhibition results from the opening of a switch located

betweenthe chargepumpand thefilter (see Figure 9).

The VCO uses an external RC network. It delivers

a linear sawtooth obtained by the charge and the

discharge of the capacitor, with a current propor-

tionnal to the current in the resistor. The typical

thresholds of the sawtooth are 1.6V and 6.4V.

TDA9110

16/29

TDA9110 Datasheet(PDF) 16 Page - STMicroelectronics

TDA9110 Datasheet(HTML) 16 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL