AD7357 datasheet(18/20 Pages) AD

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AD7357

Preliminary Technical Data

Rev. PrF | Page 18 of 20

SERIAL INTERFACE

Figure 30 shows the detailed timing diagram for serial

interfacing to the AD7357. The serial clock provides the

conversion clock and controls the transfer of information from

the AD7357 during conversion.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS puts the track and hold into hold mode at

which point the analog input is sampled and the bus is taken

out of three-state. The conversion is also initiated at this point

and requires a minimum of 16 SCLKs to complete. Once 15

SCLK falling edges have elapsed, the track and hold goes back

into track on the next SCLK rising edge, as shown in Figure 30

at Point B. On the rising edge of CS, the conversion will be

terminated and SDATAA and SDATAB go back into three-state.

If CS is not brought high, but is instead held low for a further

16 SCLK cycles on SDATAA, the data from the conversion on

ADCB are output on SDATAA.

Likewise, if CS is held low for a further 16 SCLK cycles on

SDATAA, the data from the conversion on ADC A is output on

SDATAB (see Figure 31). In this case, the SDATA line in use

goes back into three-state on the 32nd SCLK falling edge or the

rising edge of CS, whichever occurs first.

A minimum of 16 serial clock cycles are required to perform

the conversion process and to access data from one conversion

on either data line of the AD7357. CS going low provides the

leading zero to be read in by the microcontroller or DSP. The

remaining data is then clocked out by subsequent SCLK falling

edges, beginning with a second leading zero. Thus, the first

falling clock edge on the serial clock has the leading zero

provided and also clocks out the second leading zero. The 14-bit

result then follows with the final bit in the data transfer valid on

the 16th falling edge, having being clocked out on the previous

(15th) falling edge. In applications with a slower SCLK, it may be

possible to read in data on each SCLK rising edge depending on

the SCLK frequency. The first rising edge of SCLK after the CS

falling edge would have the second leading zero provided, and

the 15th rising SCLK edge would have DB0 provided.

SCLK

DOUTA

DOUTB

2 LEADING ZEROS

THREE-

STATE

tQUIET

THREE-STATE

DB13

DB12

DB2

DB0

DB1

DB11

DB10

tACQUISITION

tCONVERT

Figure 30. Serial Interface Timing Diagram

SCLK

DOUTA

THREE-

STATE

THREE-

STATE

DB12B

DB1B

DB0B

DB13A

2 LEADING

ZEROS

DB12A DB11A

DB0A

DB13B

2 ZEROS

Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs

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