´

´

´

=

´

´

OUT

OUT

IN

OUT

Q

IN

IN

V

I

PD(out)

Efficiency(%) =

100 =

100 , I

2

I

+ I

PD(in)

V

I

(4)

(

)

OUT

IN

OUT

IN

V

Efficiency(%) =

× 100 I

= 2

I

Quiescent current was neglected.

2 × V

´

(5)

PCB LAYOUT

C2

TPS60150

Large transient currents flow in the VIN, VOUT, and GND traces. To minimize both input and output ripple, keep

the capacitors as close as possible to the regulator using short, direct circuit traces.

Figure 26. Recommended PCB Layout

Copyright © 2008, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Link(s): TPS60150