ADS6149 datasheet(21/70 Pages) TI

21 / 70 page

ADS6149/ADS6129

ADS6148/ADS6128

www.ti.com ..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008

A7–A0 IN HEX

<CLKOUT POSN> Output clock position control

LVDS Interface

D7-D5

<CLKOUT POSN> Output clock rising edge position

000

Default output clock position (refer to timing specification table)

100

Default output clock position (refer to timing specification table)

101

Rising edge shifted by + (4/26)Ts

110

Rising edge aligned with data transition

111

Rising edge shifted by - (4/26)Ts

D4-D2

<CLKOUT POSN> Output clock falling edge position

000

Default output clock position (refer to timing specification table)

100

Default output clock position (refer to timing specification table)

101

Falling edge shifted by + (4/26)Ts

110

Falling edge aligned with data transition

111

Falling edge shifted by - (4/26)Ts

CMOS Interface

D7-D5

<CLKOUT POSN> Output clock rising edge position

000

Default output clock position (refer to timing specification table)

100

Default output clock position (refer to timing specification table)

101

Rising edge shifted by + (4/26)Ts

110

Rising edge shifted by + (6/26)Ts

111

Rising edge aligned with data transition

D4-D2

<CLKOUT POSN> Output clock falling edge position

000

Default output clock position (refer to timing specification table)

100

Default output clock position (refer to timing specification table)

101

Falling edge shifted by + (4/26)Ts

110

Falling edge shifted by + (6/26)Ts

111

Falling edge aligned with data transition

Ts = 1/Sampling Frequency

A7–A0 IN HEX

<DATA FORMAT> 2s complement or offset binary

D2,D1

DFS pin controls data format selection

2's complement

Offset binary

A7–A0 IN HEX

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