DS3102_08 datasheet(21/141 Pages) MAXIM

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____________________________________________________________________________________________ DS3102

Rev: 102808

21 of 141

7.5

Input Clock Monitoring

Each input clock is continuously monitored for frequency accuracy and activity. Frequency monitoring is desribed in

Section 7.5.1, while activity monitoring is described in Sections 7.5.2 and 7.5.3. Any input clock that has a

frequency out-of-band alarm or activity alarm is automatically declared invalid. The valid/invalid state of each input

clock is reported in the corresponding real-time status bit in registers VALSR1 or VALSR2. When the valid/invalid

state of a clock changes, the corresponding latched status bit is set in registers MSR1 or MSR2, and an interrupt

request occurs if the corresponding interrupt enable bit is set in registers IER1 or IER2. Input clocks marked invalid

cannot be automatically selected as the reference for either DPLL. If the T4 DPLL does not have any valid input

clocks available, the T4NOIN status bit is set to 1 in MSR3.

7.5.1 Frequency Monitoring

The DS3102 monitors the frequency of each input clock and invalidates any clock whose frequency is outside

specified limits. Two different monitors are available: the course frequency range monitor and the high-resolution

frequency monitor. The course frequency range monitor can quickly (less than 2ms) determine whether the input

clock frequency is within approximately 10,000ppm of the target frequency. When the frequency range monitor is

enabled by setting MCR1:FREN = 1, input clocks with frequency outside the 10,000ppm limit are very quickly

disqualified.

The high-resolution frequency monitor has two frequency limits that can be specified: a soft limit and a hard limit.

For all input clocks except the T0 DPLL’s selected reference, these limits are specified in the ILIMIT register. For

the T0 DPLL’s selected reference, the limits are specified in the SRLIMIT register. When the frequency of an input

clock is greater than or equal to the soft limit, the corresponding SOFT alarm bit is set to 1 in the ISR registers. The

soft limit is only for monitoring; triggering it does not invalidate the clock. When the frequency of an input clock is

greater than or equal to the hard limit, the corresponding HARD alarm bit is set to 1 in the

ISR registers, and the

clock is marked invalid in the VALSR registers. Monitoring according to the hard and soft limits is enabled/disabled

using the HARDEN and SOFTEN bits in the MCR10 register. Both the ILIMIT and SRLIMIT registers have a default

soft limit of

±11.43ppm and a default hard limit of ±15.24ppm. Limits can be set from ±3.81ppm to ±60.96ppm in

3.81ppm steps. Both the SOFT and HARD alarm limits have hysteresis as required by GR-1244. Frequency

monitoring is only done on an input clock when the clock does not have an activity alarm.

Frequency measurements can be done with respect to the internal 204.8MHz master clock or the T0 DPLL internal

frequency, as specified by the FMONCLK bit in MCR10. Measured frequency can be read from any frequency

monitor by specifying the input clock in the FMEASIN field of MCR11 and reading the frequency from the FMEAS

7.5.2 Activity Monitoring

Each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. A leaky bucket

accumulator is similar to an analog integrator: the output amplitude increases in the presence of input events and

gradually decays in the absence of events. When events occur infrequently, the accumulator value decays fully

between events and no alarm is declared. When events occur close enough together, the accumulator increments

faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events

occur infrequently enough, the accumulator can decay faster than it is incremented and eventually reaches the

alarm clear threshold. The leaky bucket events come from the frequency range and fast activity monitors.

The leaky bucket accumulator for each input clock can be assigned one of four configurations (0 to 3) in the

BUCKET field of the ICR registers. Each leaky bucket configuration has programmable size, alarm declare

threshold, alarm clear threshold, and decay rate, all of which are specified in the LBxy registers.

Activity monitoring is divided into 128ms intervals. The accumulator is incremented once for each 128ms interval in

which the input clock is inactive for more than two cycles (more than four cycles for 155.52MHz, 156.25MHz,

125MHz, 62.5MHz, 25MHz, and 10MHz input clocks). Thus the “fill” rate of the bucket is at most 1 unit per 128ms,

or approximately 8 units/second. During each period of 1, 2, 4, or 8 intervals (programmable), the accumulator

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