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LPC2142 Datasheet(PDF) 11 Page - NXP Semiconductors

Part # LPC2142
Description  Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
PDF  40 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC2142 Datasheet(HTML) 11 Page - NXP Semiconductors

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LPC2141_42_44_46_48_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 17 November 2008
11 of 40
NXP Semiconductors
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
[1]
5 V tolerant pad (no built-in pull-up resistor) providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
[2]
5 V tolerant pad (no built-in pull-up resistor) providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If
configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[3]
Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output
functionality.
P1.26/RTCK
24[6]
I/O
P1.26 — General purpose input/output digital pin (GPIO).
I/O
RTCK — Returned Test Clock output. Extra signal added to the JTAG port.
Assists debugger synchronization when processor frequency varies.
Bidirectional pin with internal pull-up.
Note: LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate
as Debug port after reset.
P1.27/TDO
64[6]
I/O
P1.27 — General purpose input/output digital pin (GPIO).
O
TDO — Test Data out for JTAG interface.
P1.28/TDI
60[6]
I/O
P1.28 — General purpose input/output digital pin (GPIO).
I
TDI — Test Data in for JTAG interface.
P1.29/TCK
56[6]
I/O
P1.29 — General purpose input/output digital pin (GPIO).
I
TCK — Test Clock for JTAG interface. This clock must be slower than 1
⁄
6 of
the CPU clock (CCLK) for the JTAG interface to operate.
P1.30/TMS
52[6]
I/O
P1.30 — General purpose input/output digital pin (GPIO).
I
TMS — Test Mode Select for JTAG interface.
P1.31/TRST
20[6]
I/O
P1.31 — General purpose input/output digital pin (GPIO).
I
TRST — Test Reset for JTAG interface.
D+
10[7]
I/O
USB bidirectional D+ line.
D
−
11[7]
I/O
USB bidirectional D
− line.
RESET
57[8]
I
External reset input: A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
XTAL1
62[9]
I
Input to the oscillator circuit and internal clock generator circuits.
XTAL2
61[9]
O
Output from the oscillator amplifier.
RTCX1
3[9]
I
Input to the RTC oscillator circuit.
RTCX2
5[9]
O
Output from the RTC oscillator circuit.
VSS
6, 18, 25, 42,
50
I
Ground: 0 V reference.
VSSA
59
I
Analog ground: 0 V reference. This should nominally be the same voltage
as VSS, but should be isolated to minimize noise and error.
VDD
23, 43, 51
I
3.3 V power supply: This is the power supply voltage for the core and I/O
ports.
VDDA
7I
Analog 3.3 V power supply: This should be nominally the same voltage as
VDD but should be isolated to minimize noise and error. This voltage is only
used to power the on-chip ADC(s) and DAC.
VREF
63
I
ADC reference voltage: This should be nominally less than or equal to the
VDD voltage but should be isolated to minimize noise and error. Level on this
pin is used as a reference for ADC(s) and DAC.
VBAT
49
I
RTC power supply voltage: 3.3 V on this pin supplies the power to the RTC.
Table 3.
Pin description …continued
Symbol
Pin
Type
Description



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