LPC2361 datasheet(28/50 Pages) NXP

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LPC2361_62_3

Product data sheet

Rev. 03 — 11 November 2008

28 of 50

NXP Semiconductors

LPC2361/62

Single-chip 16-bit/32-bit MCU

7.23.3 Wake-up timer

The LPC2361/62 begins operation at power-up and when awakened from Power-down

mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to

resume quickly. If the main oscillator or the PLL is needed by the application, software will

need to enable these features and wait for them to stabilize before they are used as a

clock source.

When the main oscillator is initially activated, the wake-up timer allows software to ensure

that the main oscillator is fully functional before the processor uses it as a clock source

and starts to execute instructions. This is important at power on, all types of Reset, and

whenever any of the aforementioned functions are turned off for any reason. Since the

oscillator and other functions are turned off during Power-down mode, any wake-up of the

processor from Power-down mode makes use of the wake-up Timer.

The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin

code execution. When power is applied to the chip, or when some event caused the chip

to exit Power-down mode, some time is required for the oscillator to produce a signal of

sufﬁcient amplitude to drive the clock logic. The amount of time depends on many factors,

including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its

electrical characteristics (if a quartz crystal is used), as well as any other external circuitry

(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient

conditions.

7.23.4 Power control

The LPC2361/62 supports a variety of power control features. There are three special

modes of processor power reduction: Idle mode, Sleep mode, and Power-down mode.

The CPU clock rate may also be controlled as needed by changing clock sources,

reconﬁguring PLL values, and/or altering the CPU clock divider value. This allows a

trade-off of power versus processing speed based on application requirements. In

addition, Peripheral Power Control allows shutting down the clocks to individual on-chip

peripherals, allowing ﬁne tuning of power consumption by eliminating all dynamic power

use in any peripherals that are not required for the application. Each of the peripherals

has its own clock divider which provides even better power control.

The LPC2361/62 also implements a separate power domain in order to allow turning off

power to the bulk of the device while maintaining operation of the RTC and a small SRAM,

referred to as the battery RAM.

7.23.4.1

Idle mode

In Idle mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Idle mode and may generate

interrupts to cause the processor to resume execution. Idle mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.23.4.2

Sleep mode

In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The

processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Sleep mode and the logic levels of chip pins remain static. The

output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The

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