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PCA9544A Datasheet(PDF) 16 Page - NXP Semiconductors |
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PCA9544A Datasheet(HTML) 16 Page - NXP Semiconductors |
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16 / 27 page  PCA9544A_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 24 November 2008 16 of 27 NXP Semiconductors PCA9544A 4-channel I2C-bus multiplexer with interrupt logic 11. Dynamic characteristics [1] Pass gate propagation delay is calculated from the 20 Ω typical R on and the 15 pF load capacitance. [2] After this period, the first clock pulse is generated. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. [5] Measurements taken with 1 k Ω pull-up resistor and 50 pF load. Table 9. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus Fast-mode I2C-bus Unit Min Max Min Max tPD propagation delay from SDA to SDn, or SCL to SCn - 0.3[1] - 0.3[1] ns fSCL SCL clock frequency 0 100 0 400 kHz tBUF bus free time between a STOP and START condition 4.7 - 1.3 - µs tHD;STA hold time (repeated) START condition [2] 4.0 - 0.6 - µs tLOW LOW period of the SCL clock 4.7 - 1.3 - µs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - µs tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 µs tSU;DAT data set-up time 250 - 100 - ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[4] 300 ns tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 µs Cb capacitive load for each bus line - 400 - 400 µs tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tVD;DAT data valid time HIGH-to-LOW [5] -1 - 1 µs LOW-to-HIGH [5] - 0.6 - 0.6 µs tVD;ACK data valid acknowledge time - 1 - 1 µs INT tv(INTnN-INTN) valid time from INTn to INT signal [5] -4 - 4 µs td(INTnN-INTN) delay time from INTn to INT inactive [5] -2 - 2 µs tw(rej)L LOW-level rejection time INTn inputs [5] 1- 1 - µs tw(rej)H HIGH-level rejection time INTn inputs [5] 0.5 - 0.5 - µs |
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