PCA9634D datasheet(13/38 Pages) NXP

13 / 38 page

PCA9634_6

Product data sheet

Rev. 06 — 12 September 2008

13 of 38

NXP Semiconductors

PCA9634

8-bit Fm+ I2C-bus LED driver

7.3.4 GRPPWM: Group duty cycle control

When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz ﬁxed frequency

signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is

then used as a global brightness control allowing the LED outputs to be dimmed with the

same value. The value in GRPFREQ is then a ‘Don’t care’.

General brightness for the 8 outputs is controlled through 256 linear steps from 00h

(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1

registers).

When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers

deﬁne a global blinking pattern, where GRPFREQ contains the blinking period (from

24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

(2)

7.3.5 GRPFREQ: Group frequency

GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2

Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1

registers).

Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)

to FFh (10.73 s).

(3)

Table 8.

GRPPWM - Group duty cycle control register (address 0Ah) bit description

Legend: * default value.

Address

Bit

Symbol

Access

Value

Description

0Ah

GRPPWM

7:0

GDC[7:0]

R/W

1111 1111

GRPPWM register

duty cycle

GDC 7:0

[]

256

---------------------------

Table 9.

GRPFREQ - Group Frequency register (address 0Bh) bit description

Legend: * default value.

Address

Bit

Symbol

Access

Value

Description

0Bh

GRPFREQ

7:0

GFRQ[7:0]

R/W

0000 0000*

GRPFREQ register

global blinking period

GFRQ 7:0

[] 1

---------------------------------------- in

onds

sec

()

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