AT91SAM7S256 datasheet(32/50 Pages) ATMEL

32 / 50 page

6175GS–ATARM–24-Dec-08

AT91SAM7S Series Summary

9.5

Debug Unit

• Comprises:

– One two-pin UART

– One Interface for the Debug Communication Channel (DCC) support

– One set of Chip ID Registers

– One Interface providing ICE Access Prevention

•Two-pin UART

– Implemented features are compatible with the USART

– Programmable Baud Rate Generator

– Parity, Framing and Overrun Error

– Automatic Echo, Local Loopback and Remote Loopback Channel Modes

• Debug Communication Channel Support

– Offers visibility of COMMRX and COMMTX signals from the ARM Processor

• Chip ID Registers

– Identification of the device revision, sizes of the embedded memories, set of

peripherals

– Chip ID is 0x270B0A40 for AT91SAM7S512 Rev A

– Chip ID is 0x270B0940 for AT91SAM7S256 Rev A

– Chip ID is 0x270B0941 for AT91SAM7S256 Rev B

– Chip ID is 0x270A0740 for AT91SAM7S128 Rev A

– Chip ID is 0x270A0741 for AT91SAM7S128 Rev B

– Chip ID is 0x27090540 for AT91SAM7S64 Rev A

– Chip ID is 0x27090543 for AT91SAM7S64 Rev B

– Chip ID is 0x27080342 for AT91SAM7S321 Rev A

– Chip ID is 0x27080340 for AT91SAM7S32 Rev A

– Chip ID is 0x27080341 for AT91SAM7S32 Rev B

– Chip ID is 0x27050241 for AT9SAM7S161 Rev A

– Chip ID is 0x27050240 for AT91SAM7S16 Rev A

Note:

Refer to the errata section of the datasheet for updates on chip ID.

9.6

Periodic Interval Timer

• 20-bit programmable counter plus 12-bit interval counter

9.7

Watchdog Timer

• 12-bit key-protected Programmable Counter running on prescaled SCLK

• Provides reset or interrupt signals to the system

• Counter may be stopped while the processor is in debug state or in idle mode

9.8

Real-time Timer

• 32-bit free-running counter with alarm running on prescaled SCLK

• Programmable 16-bit prescaler for SLCK accuracy compensation

AT91SAM7S256 Datasheet(PDF) 32 Page - ATMEL Corporation

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