CS5366 datasheet(15/41 Pages) CIRRUS

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DS626F3

CS5366

SERIAL AUDIO INTERFACE - I²S/LJ TIMING

The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.

Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.

Notes:

Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System

Clocking” on page 10.

CLKMODE functionality described in Section 4.6.3

"Master Mode Clock Dividers" on page 24.

In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, chip performance

is guaranteed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page

25.

Figure 3. I²S/LJ Timing

Parameter

Symbol

Min

Typ

Max

Unit

Sample Rates

Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

108

216

kHz

Master Mode

SCLK Frequency

SCLK Period

1/(64*216 kHz)

SCLK Duty Cycle (Note 1)

(CLKMODE = 0)(Note 2)

(CLKMODE = 1)(Note 2)

tPERIOD

tHIGH

64*Fs

72.3

64*Fs

LRCK setup

before SCLK rising

LRCK hold

after SCLK rising

tSETUP1

tHOLD1

SDOUT setup

before SCLK rising

SDOUT hold

after SCLK rising (VLS = 1.8 V)

after SCLK rising (VLS = 3.3 V)

after SCLK rising (VLS = 5 V)

tSETUP2

tHOLD2

Slave Mode

SCLK Frequency (Note 3)

SCLK Period

1/(64*216 kHz)

SCLK Duty Cycle

tPERIOD

tHIGH

72.3

64*Fs

LRCK setup

before SCLK rising

LRCK hold

after SCLK rising

tSETUP1

tHOLD1

SDOUT setup

before SCLK rising (VLS = 1.8 V)

before SCLK rising (VLS = 3.3 V)

before SCLK rising (VLS = 5 V)

SDOUT hold

after SCLK rising (VLS = 1.8 V)

after SCLK rising (VLS = 3.3 V)

after SCLK rising (VLS = 5 V)

tSETUP2

tHOLD2

LRCK

SDOUT

SCLK

data

channel

data

HOLD2

SET UP2

HOLD1

SET UP1

PERIOD

HIGH

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