AT25DF081 datasheet(4/38 Pages) ATMEL

4 / 38 page

3674E–DFLASH–8/08

AT25DF081

Block Diagram

Memory Array

To provide the greatest flexibility, the memory array of the AT25DF081 can be erased in four lev-

els of granularity including a full chip erase. In addition, the array has been divided into physical

sectors of uniform size, of which each sector can be individually protected from program and

erase operations. The size of the physical sectors is optimized for both code and data storage

applications, allowing both code and data segments to reside in their own isolated

regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the break-

down of each physical sector.

Figure 2-1.

8-SOIC Top View

Figure 2-2.

8-UDFN Top View

Figure 2-3.

11-dBGA (Top View

Through Back of Die)

GND

VCC

HOLD

SCK

GND

VCC

HOLD

SCK

234

VCC

HOLD

SCK

GND

FLASH

MEMORY

ARRAY

Y-GATING

SCK

Y-DECODER

X-DECODER

I/O BUFFERS

AND LATCHES

CONTROL AND

PROTECTION LOGIC

SRAM

DATA BUFFER

INTERFACE

CONTROL

AND

LOGIC

HOLD

AT25DF081 Datasheet(PDF) 4 Page - ATMEL Corporation

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