9202 datasheet(88/175 Pages) STMICROELECTRONICS

88 / 175 page

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

88/175

DDC2B Protocol

DDC2B is constructed based on the Philips I2C in-

terface. However, in the level of DDC2B, PC host

is fixed as the master and the monitor is always re-

garded as the slave. Both master and slave can be

operated as a transmitter or receiver, but the mas-

ter device determines which mode is activated. In

this protocol, address pointer is also used.

According to DDC2B specification, A0 (for WRITE

Mode) and A1 (for READ Mode) are assigned as

the default address of monitors.

The reception of the incoming data in WRITE

Mode or the updating of the outgoing data in

READ Mode should be finished within the speci-

fied time limit. If software in the slave’s side cannot

react to the master in time, based on I2C protocol,

SCL pin can be stretched low to inhibit the further

action from the master. The transaction can be

proceeded in either byte or burst format.

Figure 43. Conceptual Structure of the DDC Interface

AI06645

DDC Interrupt

vector address

(

0023H

)

DDC2B/DDC2AB

Utilities

DDC2B

Utilities

DDC1.DDC2B

Utilities

Check Mode flag in DDCCON

Mode = 1 Mode = 1 Mode = 0

I2C

ServiceRoutines

I2C interface

(H/W)

DDC Transmitter

(H/W)

DDC2B/DDC2AB

commandreceived

DDC2B

SWENB =1

SWENB =0

SWENB =1

9202 Datasheet(PDF) 88 Page - STMicroelectronics

9202 Datasheet(HTML) 88 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL